1. Field of the Invention
This invention relates to computer control of work flow in a manufacturing production line and more particularly to automation of production control of a manufacturing process by improved automation of scheduling of work.
2. Description of Related Art
In the manufacture of integrated circuit semiconductor devices, semiconductor wafer dispatching used to be controlled by the C/R (Critical Ratio) that indicates the degree of customer dissatisfaction. The overall slack time in the front end of the line (near the beginning of the production line) procedure is greater compared to that in the rear end of the line (near the finishing end of the production line) procedure revealing that the machine in the rear end of the line are overloaded by a rush order.
The manufacturing process involved in integrated circuit (IC) fabrication is complex and unique. A wafer may return to be processed by the same manufacturing tool, i.e. machine, several times and the wafer can return repeatedly to the same stage for different processes that construct a flexible but sophisticated module and a re-entrant process flow in this environment, for use in production scheduling, there are several factors which to be used to measure performance. Such measures of performance are machine utilization, throughput, due date and stage cycle time. Many dispatching rules have therefore been developed to fulfill the objective.
Research on efficient scheduling policies to reduce mean and variance of cycle-time and variance of cycle-time in semiconductor manufacturing plants has compared several scheduling policies for reducing mean and variance of cycle time. An experimental model comprising a single product with an IC manufacturing re-entrant process showed that the fluctuation smoothing policy--least slack policy indicates improved performance. A scheduling method has been tried using the first in first out (FIFO) policy. Most of the research is based upon an environment which is slightly different from a real case.
Yoshida et al U.S. Pat. No. 5,219,765 "Method for Manufacturing a Semiconductor Device Including Wafer Aging, Probe Inspection, and Feeding Back the Results of the Inspection to the Device Fabrication Process" describes a method for manufacturing semiconductor devices including a test from which information is fed back into the fabrication process for improvement.
Friedman et al U.S. Pat. No. 5,240,866 "Method for Characterizing Failed Circuits on Semiconductor Wafers" shows a method for characterizing failed circuits on semiconductor wafers.
Kobayashi et al U.S. Pat. No. 5,210,041 "Process for Manufacturing Semiconductor Integrated Circuit Device" shows computer control of testing/feedback to a chip manufacturing process.